The present invention relates to nonvolatile semiconductor memories.
A NAND type of flash EEPROM having such a memory cell array as shown in FIG. 1 has been hitherto known as one of nonvolatile semiconductor memories.
The memory cell array of the NAND flash EEPROM is composed of a number of NAND cell units. Each of the NAND cell units has a NAND series of memory cells (e.g., 16 memory cells), a source-side select gate transistor connected between one end of the NAND series of memory cells and a source line, and a drain-side select gate transistor connected between the other end of the NAND string and a bit line BLi.
The memory cell array is composed of a plurality of blocks BLkj. Control gate electrodes (word lines) CG0 to CG15, source-side select gate electrodes SGS, and drain-side select gate electrodes SGD extend in the row direction, while bit lines BLi extend in the column direction. A plurality of memory cells M0 to Mi connected to one word line forms a unit called PAGE.
Usually a page of data is read out in a single read operation. The read page of data is latched by a latch circuit and then output serially to the outside of the memory chip.
For such a NAND flash EEPROM it is important to obtain a large storage capacity and reduce the area of the memory cell array for small chip sizes. To this end, it is required to reduce the size of memory cells and the spacing between two adjacent select gate lines (electrodes).
Usually the select gate line is provided with contact areas, which are large in area and prevent the spacing between two adjacent select gate lines from being reduced. When, in patterning the contact areas, misalignment occurs between the select gate line and the contact area due to resist misalignment, the resistance of the select gate line increases.
To the contact areas of the select gate line is connected a select gate bypass line, which is formed on an interlayer insulator on the word line (control gate line). In this case, in a read operation, capacitive coupling between the select gate bypass line and the word line may cause the potential on the selected word line in a selected block to rise in error.